module top(
           input clk,
           input rst_n,
           input key_in,

           output key_out
       );
parameter cnt_max = 32'd149999;

reg [31: 0] cnt_down;
reg [31: 0] cnt_up;

wire cnt_start;
reg key_in_r;

assign cnt_dstart = key_in_r & ~key_in; //按下
assign cnt_ustart = ~key_in_r & key_in; //松开

assign	key_out = ((cnt_down == cnt_max) && (key_in_r == 1'b0)) ? 1'b0 : (((cnt_up == cnt_max) && (key_in_r == 1'b1)) ? 1'b1 : key_out);

always@(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			begin
				cnt_down <= 32'd0;
				cnt_up <= 32'd0;
				key_in_r <= 1'b0;
			end
		else
			begin
				cnt_down <= (cnt_down == cnt_max) ? ((cnt_dstart) ? 32'd0 : cnt_down) : cnt_down + 1'b1;
				cnt_up <= (cnt_up == cnt_max) ? ((cnt_ustart) ? 32'd0 : cnt_up) : cnt_up + 1'b1;
				key_in_r <= key_in;
			end
	end
endmodule

// cnt<=(cnt==cnt_max)?((start)?1'b0:cnt):cnt+1'b1;